Intel Diamond Rapids to boost core counts to 192, but RIP Hyperthreading

Intel has unveiled its upcoming Diamond Rapids Xeon processor, which will feature a significant increase in core count to 192, marking a 50 percent rise over its predecessor. However, this boost in cores comes with a notable reduction in thread count, as Intel has decided to discontinue Hyperthreading—its implementation of simultaneous multithreading (SMT)—on this generation of Xeon chips. Despite SMT’s long history since 2002 and its ability to improve performance in certain workloads, Intel is stepping away from the technology for now, though it plans to reinstate SMT with the subsequent Coral Rapids Xeon. Diamond Rapids will be manufactured using Intel’s advanced 18A-P process, a refined 2nm-class technology, and will employ a multi-die design reminiscent of AMD’s Epyc processors. The chip architecture includes two I/O dies paired with four vertically stacked compute chiplets, each containing 48 cores, connected through Intel’s Foveros 3D packaging technology. This design mirrors trends in the industry toward chiplet-based processors, which allow for greater scalability and efficiency. The L3 cache is expected to be centralized on the base die, freeing up space on the compute chiplets, although the exact placement of the memory controller remains unclear. Intel’s move to increase core counts while temporarily dropping SMT reflects ongoing competition with AMD, which is pushing even higher core counts with its 256-core Venice Epyc processors, potentially launching earlier than Diamond Rapids’ expected 2027 release. The architectural similarities between Diamond Rapids and other recent designs, such as Fujitsu’s Monaka, highlight a broader industry shift toward modular, chiplet-based CPUs that balance performance, power, and manufacturing complexity. This development is significant as it signals Intel’s strategic priorities in the server CPU market, focusing on raw core counts and advanced packaging technologies while experimenting with threading approaches. The temporary removal of Hyperthreading may impact workloads that benefit from SMT, but Intel’s planned reintroduction of the technology in future generations suggests an adaptive approach to evolving performance demands.